Positron raises $875M at $5B valuation for its memory-first AI inference chips

On September 10, 2026, Positron AI announced an $875 million Series C financing at a $5 billion post-money valuation to fund the tapeout of its next-generation inference silicon (Asimov), a 2 MW+ engineering data center and emulation platform, and the production ramp of its Titan inference system (PRNewswire release, 09:00 ET; Reuters).

The financing was raised in two tranches (CONFIRMED by PRNewswire and Reuters):

• Series C: $375M at a $3.5B pre-money valuation — co-led by NEA, Andra Capital, Atreides Management, Valor Equity Partners, and Dylan Patel's SemiAnalysis Capital.
• Series C-1: up to $500M — led by NEA and Jim Clark (co-founder of Silicon Graphics and Netscape).

Additional investors: DFJ Growth, Qatar Investment Authority (QIA), Resilience Reserve, Arena Private Wealth, Natural Capital, Helena, 1517 Fund, Flume Ventures, Unless, Boardman Bay Capital Management, Fincadia Advisors, Banyan Ventures and U First Capital; strategic investors VentureTech Alliance, Hudson River Trading (HRT), Cisco Investments and Naver Ventures (tying Positron to South Korea's Naver).

Board additions from the round: Forest Baskett (NEA), Gavin Baker (Atreides Management), Thomas Jermoluk (Jim Clark Office), and Dylan Patel (SemiAnalysis) joined Positron's board of directors (FACT, PRNewswire).

What the money funds (FACT, per the release): (1) full funding of the Asimov tapeout on TSMC N3P at the end of 2026, with production in the second half of 2027; (2) bring-up of a 2 MW+ engineering data center and emulation platform; (3) production ramp of Titan (4–8 Asimov chips per system, designed for models beyond 16 trillion parameters and 10M+ token contexts in a single node, scaling to thousands of nodes), including LPDDR5X supply commitments, production capacity, system integration, and go-to-market expansion.

Timeline context (FACT): Positron was founded April 2023 by Thomas Sohmers (CTO) and Edward Kmett (chief scientist), with Mitesh Agrawal (ex-Lambda COO) as CEO. Atlas — its FPGA-based inference appliance (8x Altera Agilex-7M Archer accelerators, 2,000W) — has shipped since 2024 and is deployed at hyperscaler scale, including 50+ racks at Oracle Cloud Infrastructure (OCI), with Parasail (SnapServe), Jump Trading, and i3d.net as named production customers; Cloudflare was reported evaluating it in 2025.

ISA correction (repeated for emphasis): the chips are ARM-based (ARMv9 on-chip cores in Asimov), not RISC-V; Atlas uses Altera FPGAs; hosts are AMD EPYC. See §1.

Discovery record (what_changed): "Positron raised $875M across Series C/C-1 at a $5B valuation for its RISC-V-based AI inference accelerators targeting power-efficient datacenter inference."

Validation: the funding facts are accurate and confirmed — $875M across two tranches, $5B post-money, power-efficient datacenter inference. The "RISC-V-based" descriptor is wrong (see §1): Asimov carries ARMv9 cores; the ISA-independent way to describe the thesis is "memory-first" (LPDDR5X instead of HBM). No other element of the discovery summary is contradicted.

What materially changed with this event:

• Valuation step-change: from a $1.06B valuation (Feb 2026 Series B, per PitchBook via Reuters) to $5B in seven months — roughly 4.7x. Reuters headlines "more than quadrupling"; Forkast and SiliconANGLE say "roughly five-fold"; the difference is rounding of the same ratio (minor discrepancy, flagged in §14).
• Capital scale: $875M makes this one of the largest VC rounds of the year in AI inference silicon and takes Positron's cumulative disclosed funding past ~$1.19B (seed $12.5M + $23.5M + $51.6M + $230M + $875M).
• Tranche-price nuance: the two tranches were not priced alike — $3.5B pre-money for the Series C implies a ~$3.875B post at close; describing the round as "$5B post-money" implies the Series C-1 was priced off roughly $4.5B pre-money, i.e., ~$625M of appreciation between tranches announced the same day (The Clarity's arithmetic; INTERPRETATION — Positron has not published tranche-level prices).
• Schedule slip (flagged): the Feb 2026 Series B release targeted production "in early 2027"; the Sept 2026 release says "second half of 2027" — a slip of at least two quarters booked before tapeout (The Clarity; corroborated by comparing the two press releases). EE Times (Feb 2026) had reported tapeout "toward the end of the third quarter" with samples at end of Q1 2027.
• Strategic-capital signal: Cisco Investments, Hudson River Trading, Naver Ventures and VentureTech Alliance joined as strategics, and QIA returned — a validation signal the company itself frames as de-risking the roadmap.
• Memory-thesis momentum: the raise landed two days after Qualcomm and Amazon disclosed a multi-generational LPDDR inference partnership (up to $60B in purchases per AI Market Watch) — an independent, much larger vote for the commodity-LPDDR inference thesis Positron is betting on.

Before (through Feb 2026). Positron was a $1B+ valuation FPGA-first inference vendor: Atlas shipping on Altera Agilex-7M FPGAs with HBM+DDR5, ~93% claimed memory-bandwidth utilization, U.S. fabrication, ~50-person team; Asimov ASIC designed in-house (22-person ASIC team) with a roadmap targeting tapeout late 2026 and production early 2027; customers included OCI (Parasail), Jump Trading, i3d.net; HBM/CoWoS supply chains tightening; inference emerged as the market's center of gravity.

Change (Sept 10, 2026). Positron raises $875M in two tranches at a $5B post-money valuation (≈4.7x in seven months); NEA and Jim Clark lead the C-1; four heavyweight board seats added; capital fully funds the Asimov N3P tapeout, a 2 MW+ engineering datacenter/emulation platform, and the Titan production ramp including LPDDR5X supply commitments; production date slips to 2H 2027; strategic investors (Cisco, HRT, Naver, VTA) attached; QIA returns; the company publicly restates its "memory-first, no-HBM/no-CoWoS" architecture and its simulation-based claims (>90% realized bandwidth; 5x tokens/$ and /W vs NVIDIA Rubin; 400W vs Rubin's 2.3kW).

After (as of window close Sept 17, 2026). Positron is a $5B, ~$1.19B-raised, inference-only silicon challenger with shipping product (Atlas at OCI), a fully funded ASIC tapeout this year, and production silicon due 2H 2027 — competing directly in the window when NVIDIA ships Rubin and AMD expands MI400. The "memory-first, LPDDR, air-coolable, brownfield-friendly" architecture is now one of at least three visible vectors (with OpenAI's Jalapeño and DeepSeek's V4.1 Flash CED) challenging the HBM/CoWoS-dominated "compute landlord" model of AI infrastructure.

Positron's thesis: transformer inference is memory-bound, not compute-bound — the bottleneck is feeding data to arithmetic units, not the arithmetic itself (FACT as company architecture statement; COMPANY CLAIM as performance thesis).

Shipping product — Atlas (FACT, ~93% utilization is COMPANY CLAIM validated in-part by customer quotes):

• 4U/2U appliance, 8x "Archer" accelerator cards based on Altera Agilex-7M FPGAs (32GB HBM2e each + DDR5), dual AMD EPYC Genoa 9374F host CPUs, 2,000W system power, air-cooled.
• Software: Positron Inference Engine; OpenAI-API-compatible endpoint; maps any HuggingFace Transformers model; claims <40-min setup; 93% realizable memory-bandwidth utilization vs 10–30% for GPUs.

Next-gen silicon — Asimov (FACT as disclosed spec; all performance numbers are cycle-accurate simulation, COMPANY CLAIM):

• TSMC N3P, tapeout end of 2026, production 2H 2027; organic substrate (no CoWoS).
• Memory-first: 288 GB to 2,304 GB of LPDDR5X per chip (vs 288GB HBM4 on NVIDIA Rubin; ~2–29x capacity vs H100/H200/Rubin depending on configuration — Forkast comparison); custom memory module said to deliver ~10x the bandwidth of conventional LPDDR5X interfaces (NEA blog); 2.76 TB/s "realizable memory bandwidth"; >90% realized utilization claim; commodity memory avoids HBM allocation risk (LPDDR >30% of DRAM bit supply vs ~9% for HBM — NEA blog).
• Compute/control: 512×128 systolic array at 2 GHz (TransWarp Engine) with co-located weight memory, dynamically reconfiguring to 128×512 for memory-bound attention (GEMV); dedicated streaming-vector units for softmax, RMSNorm, RoPE, SwiGLU at line rate; multiple on-chip ARMv9 64-bit CPU cores for orchestration and programmability.
• Interconnect: PCIe Gen 6 x32 host interface with CXL; 16 Tbps point-to-point chip-to-chip per link (32 Tbps bidirectional per NEA blog), switchless fabric scaling to 16,384 chips (ring/torus/mesh); dual-hemisphere architecture; ~400W TDP; air or liquid cooled.
• Credo "Weaver" memory-fanout chiplet co-development (20 chiplets per Asimov) enabling high-bandwidth LPDDR connectivity (EE Times, Feb 2026).

System — Titan (FACT as disclosed spec):

• 4 or 8 Asimov chips per node; up to 18.4TB accelerator-attached memory; up to 6TB host memory; up to ~23.7TB/s system memory bandwidth; targets models beyond 16T parameters (up to 32T per Titan page) and 10M+ token contexts in a single node; air or liquid cooled.

Claimed economics (COMPANY CLAIM, simulated): on the Positron homepage comparisons vs NVIDIA Blackwell GB300 NVL72 — 2.4x tokens/$ at 100 tokens/sec/user; 26x tokens/$ at Blackwell's max 170 tok/s/user; 4.1x faster at equal tokens/$ (400 vs 97 tok/s); "24.8x revenue per TCO dollar" against Blackwell at 400 vs 170 tok/s with a 2x premium-tier price; 5x tokens per dollar and per watt vs NVIDIA Rubin at 400W vs 2.3kW (NEA blog, Series B release). All Asimov figures trace to cycle-accurate simulations — none from production silicon (The Clarity, NEA blog, positron.ai).

• A four-fold-plus valuation jump in seven months for an ARM/LPDDR inference bet is a strong market signal that inference — not training — is where AI capital is heading, and that investors believe post-NVIDIA inference will be won on tokens-per-dollar and tokens-per-watt rather than raw FLOPs (FACT: Reuters, Forkast).
• It publicly prices the "memory-first" thesis. If Asimov delivers anywhere near its simulated >90% realized bandwidth at LPDDR cost, the most expensive subsystem in the inference stack (HBM + CoWoS) can be attacked with commodity DRAM. The round lands days after Qualcomm–Amazon's up-to-$60B LPDDR inference agreement (AI Market Watch), an independent validation of the same memory thesis.
• It changes the "compute landlord" calculus. Forkast frames Positron alongside OpenAI's Jalapeño (lab-designed silicon) and DeepSeek's V4.1 Flash CED (architecture-level cost cuts) as three simultaneous vectors eroding the NVIDIA-HBM axis.
• Strategic-investor breadth (Cisco, HRT, Naver, QIA, VTA) shows non-GPU-capital and non-US capital aligning around an alternative inference supply chain — including a sovereign (Qatar) returning across rounds and an Asia-Pacific strategic (Naver).
• ISA footnote that matters for accuracy: this is an ARM-core design (with Arm itself an investor in Positron's Series B), not RISC-V — relevant to ISA-licensing, national-security, and open-hardware narratives (see §1 correction).

• A fully funded path from FPGA revenue product (Atlas) to custom N3P ASIC (Asimov) without further dilution before production — tapeout fully funded, LPDDR5X supply commitments secured, go-to-market funded.
• A single-node 16T–32T-parameter inference box with 10M+ token contexts by 2027 — a "superintelligence-in-a-box" class capability that previously implied multi-node GPU clusters.
• Brownfield deployment: air-coolable, standard-power racks; no liquid cooling, no CoWoS, and commodity DRAM — inference capacity inside existing facilities that cannot host liquid-cooled HBM clusters (Forkast).
• An independent alternative to the HBM/CoWoS supply chain for inference workloads, at a moment when HBM4 allocation is the industry's tightest constraint.
• For Naver/HRT/Cisco as strategics: a dedicated, efficient inference supply line (Naver's strategic-compute relationship; HRT's latency-sensitive trading workloads; Cisco's networking go-to-market synergy).

• Will Asimov tape out at end of 2026 on schedule, and what do first silicon measurements show for realized bandwidth/utilization vs the 2.76 TB/s simulated figure?
• Was the Series C-1 priced at ~$4.5B pre-money (implied by "$5B post-money" arithmetic), and how much of the up-to-$500M tranche is closed vs committed?
• What revenue is Atlas generating at OCI/Parasail/Jump/i3d.net today, and how much capacity is contracted?
• Which frontier customers beyond the named strategics (Naver, HRT, Cisco) have committed to Titan/Asimov volume?
• Does the Qualcomm–Amazon LPDDR partnership (up to $60B) crowd out or validate Positron's LPDDR5X supply position (memory vendors' allocation, pricing)?
• How does NVIDIA respond on price/availability for inference-tier SKUs, and does Rubin's 288GB HBM4 narrow Positron's capacity advantage (2x, not 29x, vs Rubin)?
• What is the software maturity (kernels, quantization, multi-chip scaling to 16,384 chips) — everything hinges on the Inference Engine, which is under-documented publicly.
• Does the "Made in America" supply line extend to Asimov (TSMC N3P fab location unspecified), and how do export-control/CHIPS-era rules interact with Naver/QIA strategic shares?

• Late 2026: Asimov tapeout on TSMC N3P (company target; end of Q4) — first real milestone that will either validate or stress the roadmap; watch for tapeout confirmation and any schedule movement.
• 2H 2027: Asimov production and first Titan systems; NVIDIA Rubin and AMD MI400 will be ramping in the same window — expect intensive independent benchmarking (The Register, SemiAnalysis, etc.).
• Near-term disclosures to watch: tranche-close confirmations (was the full "up to $500M" C-1 drawn?), OCI/Atlas capacity announcements, further strategic customers, and any revenue disclosures.
• Memory-market follow-on: watch whether the Qualcomm–Amazon LPDDR deal and Positron together push memory vendors to allocate more LPDDR capacity to inference modules, and whether the HBM shortage narrative softens as a result.
• Competitive response: expect NVIDIA inference-tier price/productization (and possibly an inference-lite SKU) and more "memory-first" entrants; expect AMD/Tenstorrent/Groq messaging to engage Positron's claims directly.
• Researcher's correction to carry forward: downstream synthesis must use "ARM-based, memory-first inference silicon" — not "RISC-V" — when describing Positron.

Positron's $875M at $5B is a genuine bellwether: in seven months the market re-priced an inference-only, ARM/LPDDR "memory-first" challenger four-fold-plus on the strength of a shipping FPGA product, a funded N3P tapeout, and a compelling simulation story. The round is significant both for what it funds (a real, if slipped, path to 2027 production silicon) and for what it signals (capital now believes inference economics — tokens per dollar and per watt — can be re-won with commodity memory against the HBM/CoWoS axis). The honest framing for readers: this is a $5B bet on an unproven part, as much concentration of conviction as validation — and the story's one hard factual trap is the ISA label: Positron is ARM-core, not RISC-V. Report the money as confirmed, the architecture as disclosed-but-unmeasured, and the 2027 production date as the moment of truth.

Key evidence labels used in this analysis: FACT (independently corroborated, e.g., round size, valuation, tranches, roadmap dates, ISA/ARM core disclosure), COMPANY CLAIM (Positron performance/utilization/economics figures from simulations and press release), INDEPENDENT EVIDENCE (Reuters, QIA, NEA, EE Times, and trade-press corroboration of facts; Jump Trading latency quote; PitchBook valuation mark), INTERPRETATION (tranche-pricing arithmetic, strategic meaning, market signaling), PREDICTION (§20 timeline expectations).